(A) Field of the Invention
The present invention relates to a method for preparing a trench capacitor structure, and more particularly, to a method for preparing a trench capacitor structure capable of preventing current leakage due to the conduction of a parasitic transistor.
(B) Description of the Related Art
A memory unit of a dynamic random access memory (DRAM) includes an access transistor and a storage capacitor, wherein a source of the access transistor is connected to a top electrode of the storage capacitor, and a bottom electrode of the storage capacitor is connected to a positive voltage. In particular, as the quantity of charges stored on the capacitor becomes greater, the occurrence of read error by a read amplifier caused by noises can be greatly reduced. Therefore, memory units of current DRAM designs usually adopt a stacked capacitor of three-dimensional structure or a trench capacitor structure to increase the accumulated charges on the capacitor.
The current leakage phenomenon of the memory unit of the DRAM may decrease the charges stored on the capacitor, and the capacitor must be periodically refreshed to avoid data storage error caused by the excessive decrease of the stored charges. However, additional refresh operations may cause more power consumption of the DRAM. Therefore, the current leakage phenomenon greatly influences the electrical performance of the DRAM.